/*
 *  test_iaf_min_delay_simblocks.sli
 *
 *  This file is part of NEST.
 *
 *  Copyright (C) 2004 The NEST Initiative
 *
 *  NEST is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  NEST is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with NEST.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

 /* BeginDocumentation
Name: testsuite::test_iaf_min_delay_simblocks - sli script for testing block wise simulation

Synopsis: (test_iaf_min_delay_simblocks) run -> compares results for different min_delays


Description:

  The simulation is run with a range of different min_delays. All
  should give identical results. This is achieved by sampling the
  membrane potential at a fixed interval.

  The test is identical to test_iaf_min_delay_set except that the
  simulation is carried out by 20 subsequent calls of Simulate()
  instead of only a single one.

  Other test scripts discuss the various aspects of this script in detail,
  see the SeeAlso key below. If this test fails go back to the simpler ones.

Author:  July 2004, Diesmann, January 2005, Plesser, September 2010, Diesmann
SeeAlso: iaf_neuron, testsuite::test_iaf_i0, testsuite::test_iaf_i0_refractory, testsuite::test_iaf_dc, testsuite::test_min_delay, testsuite::test_min_delay
*/

/unittest (6335) require
/unittest using


/delay 2.0 def  % actual delay between dc generator and neuron
/h 0.1 def      % computation step size

/RunMinDelay {

  /min_del  Set      % argument: minimal delay in ms
  min_del delay leq assert  

  ResetKernel

  0 << /local_num_threads 1 /resolution h >> SetStatus

  /static_synapse <<
    /delay delay  
    /min_delay min_del
    /max_delay delay
  >> SetDefaults

%  /iaf_psc_alpha_canon Create /neuron Set
  /iaf_neuron Create /neuron Set  

  /dc_generator Create /dc_gen Set
  dc_gen <<  /amplitude 1000. >> SetStatus

  /voltmeter Create /vm Set
  vm << /withtime true >> SetStatus

  % must connect with explicit delay to assure
  % consistency as min_delay varies      
  dc_gen neuron 1.0 delay Connect

  vm neuron Connect

  1 1 21 {
  	;
  	0.5 Simulate
  } for

                  % vm samples at 1ms intervals, therefore we 
                  % get 10 data points for each min_elay if we make
                  % sure that simulation time exceeds the last required 
                  % min_delay step

  vm [/events [/times /V_m]] get cva Transpose 

} def


{
[0.1 0.2 0.3 0.4 0.5 0.6 1.0 2.0] 
 {RunMinDelay} Map 
 dup
 First exch Rest {1 index eq } Map 
 exch pop
 true exch {and} Fold 
}
assert_or_die